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ultralow power, low distortion fully differential adc d river data sheet ada4940 - 1 / ada4940 - 2 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registe red trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features small signal bandwidth: 260 mhz ultralow power 1.25ma extremely low harmonic distortion ? 122 db thd at 50 khz ? 96 db thd at 1 mhz low input voltage noise: 3.9 nv/hz 0.35 mv maximum offset voltage balanced outputs settling time to 0.1%: 34 ns rai l- to - rail output: ?v s + 0.1 v to +v s ? 0.1 v adjustable output common - mode voltage flexible power supplies: 3 v to 7 v (lfcsp) disable pin to reduce power consumption ada4940 - 1 is available in lf csp and soic packages applications low power pulsar?/sar ad c drivers single - ended - to - differential conver sion differential buffers line drivers medical i maging industrial process con trol s portable e lectronics general description the ada4940 -1 / ada4940 -2 are low noise, low distortion fully differential amplifier s with very low power consumption. they are an ideal choice for driving low power, high resolution, high performance sar and sigma- delta ( - ) analog - to -digital converters ( adcs ) with resolutions up to 16 bits from dc to 1 mhz on only 1.25 ma of quiescent current. the adjust able level of the output common - mode voltage allows the ada4940 -1 / ada4940 -2 to match the input common - mode voltage of multiple adcs. the internal common - mode feedback loop provides exceptional output balance , as well as suppression of even - order harmonic distortion products. with the ada4940 -1 / ada4940 -2 , differential gain configurations are easily realized with a simple external feedback network of four resistors determining the c losed - loop gain of the amplifier. the ada4940 -1 / ada4940 -2 are fabricated using analog devices, inc. , sige complementary bipolar process, enabling them to achi eve very low levels of distortion with an input voltage noise of only 3.9 nv /hz. the l ow dc offset and excellent dynamic performance of the ada4940 -1 / ada4940 -2 make them well suited for a variety of data acquisition and signal proces sing applications. functional block dia gram s 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 disable 10 +out 9 v ocm 5 +v s 6 +v s 7 +v s 8 +v s 15 ?v s 16 ?v s 14 ?v s 13 ?v s ada4940-1 08452-001 ada4940-2 1 ?in1 2+ fb 1 3 +v s1 4 +v s1 5? fb2 6 +in2 15 ?v s2 16 ?v s2 17 v ocm1 18 +out1 14 disable2 13 ?out2 7 ?in2 8 +fb2 9 +v s2 11 v ocm2 12 +out2 10 +v s2 21 ?v s1 22 ?v s1 23 ? fb1 24 +in1 20 disable1 19 ?out1 figure 1. 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20k 40k 60k 80k 100k 08452-300 amplitude (db) frequency (hz) +d in ?d in r1 r2 r4 r3 +in ?out c f 33? 2.5v ad7982 ada4940-1 33? 2.7nf 2.7nf c f +out + ? ?in in+ in? gnd vddref v ocm figure 2. ada4940 -1 driving the ad7982 adc the ada4940 -1 is available in a pb - free, 3 mm 3 mm , 16 - lead lfcsp , and an 8 - lead soic . the ada4940 -2 is available in a pb - free, 4 mm 4 mm , 24- lead lfcsp. the p inout is optim ized to facilitate printed circuit board ( pcb ) layout and minimize distortion. the ada4940 -1 / ada4940 -2 are specified to operate over the ? 40c to + 125 c temperature range . table 1 . similar products to the ada4940 -1 / ada4940 -2 product isupply (ma) bandwidth (mhz) slew rate (v/ s) noise ( nv/hz) ad8137 3 110 450 8.25 ada4932 -x 9 560 2800 3.6 ada4941 -1 2. 2 31 22 5.1 table 2 . com p lementary products to the ada4940 -1 / ada4940 -2 product power (mw ) throughput ( msps ) resolution (bits ) snr ( db ) ad7982 7 .0 1 18 98 ad7984 10.5 1. 33 3 18 96.5 ad7621 65 3 16 88 ad7623 45 1. 333 16 88
ada4940-1/ada4940-2 data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? v s = 5 v .......................................................................................... 3 ? v s = 3 v .......................................................................................... 5 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? maximum power dissipation ..................................................... 7 ? esd caution .................................................................................. 7 ? pin configurations and function descriptions ........................... 8 ? typical performance characteristics ........................................... 10 ? test circuits ..................................................................................... 19 ? terminology .................................................................................... 20 ? definition of terms .................................................................... 20 ? theory of operation ...................................................................... 21 ? applications information .............................................................. 22 ? analyzing an application circuit ............................................ 22 ? setting the closed-loop gain .................................................. 22 ? estimating the output noise voltage ...................................... 22 ? impact of mismatches in the feedback networks ................. 23 ? calculating the input impedance of an application circuit 23 ? input common-mode voltage range ..................................... 24 ? input and output capacitive ac coupling ............................ 25 ? setting the output common-mode voltage .......................... 25 ? disable pin .............................................................................. 25 ? driving a capacitive load ......................................................... 25 ? driving a high precision adc ................................................ 26 ? layout, grounding, and bypassing .............................................. 27 ? ada4940-1 lfcsp example .................................................... 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 29 ? revision history 3/12rev. a to rev. b reorganized layout ............................................................ universal added ada4940-1 8-lead soic package ...................... universal changes to features section, table 1, and figure 1; replaced figure 2 .............................................................................................. 1 changed v s = 2 v(or +5 v) section to v s = +5 v section ................................................................................................ 3 changes to v s = +5 v section and table 3.................................... 3 changes to table 4 and table 5 ....................................................... 4 changes to v s = 3 v section and table 6 ...................................... 5 changes to table 7 and table 8 ....................................................... 6 added figure 5 and table 12, renumbered sequentially ........... 9 changes to figure 7, figure 8, and figure 9................................ 10 added figure 15 and figure 18; changes to figure 13, figure 14, and figure 16 ................................................................ 11 changes to figure 19 and figure 20 ............................................. 12 changes to figure 25, figure 26, and figure 27; added figure 28, figure 29, and figure 30 .............................................. 13 changes to figure 31, figure 32, figure 33, figure 34, figure 35, and figure 36 ................................................................................... 14 changes to figure 37, figure38, figure 39, and figure 41 ........ 15 changes to figure 49, figure 50, and figure 51 ......................... 17 added figure 55 and figure 57..................................................... 18 changes to differential v os , differential cmrr, and v ocm cmrr section ................................................................................ 20 changes to calculating the input impedance of an application circuit section ................................................................................ 23 changes to figure 71 ...................................................................... 25 changes to driving a high precision adc section and figure 73 ................................................................................... 26 changed ada4940-1 example section to ada4940-1 lfcsp example section ............................................................................. 27 changes to ordering guide .......................................................... 29 12/11rev. 0 to rev. a changes to features section, general description section, table 1 .................................................................................. 1 replaced figure 1 and figure 2 ....................................................... 1 changes to v s = 2.5 v (or +5 v) section and table 3 ................ 3 changes to table 6 ............................................................................. 5 replaced figure 7, figure 8, figure 9, and figure 10 ................... 9 replaced figure 14, figure 15, and figure 17 ............................. 10 replaced figure 24 and figure 27 ................................................ 12 changes to figure 37 ...................................................................... 14 replaced figure 43 and figure 46 ................................................ 15 replaced figure 53 ......................................................................... 18 changes to estimating the output noise voltage section, table 14, table 15, and calculating the input impedance of an application circuit section ........................................................... 21 changes to input common-mode voltage range section....... 22 changes to driving a high precision adc section and figure 65 .......................................................................................... 24 10/11revision 0: initial version
data sheet ada4940-1/ada4940-2 re v. b | page 3 of 32 specifications v s = 5 v v ocm = mid supply , r f = r g = 1 k ?, r l, dm = 1 k ?, t a = 25c, lfcsp package, unless otherwise noted. t min to t max = ? 40 c to +1 25 c. ( see figure 61 fo r the definition of terms .) +d in or C d in to v out, dm performance table 3 . parameter test conditions /comments min typ max unit dynamic performance ? 3 db small signal bandwidth v o ut , dm = 0.1 v p -p , g = 1 260 mhz v out, dm = 0.1 v p - p, g = 2 220 mhz v out, dm = 0.1 v p - p, g = 5 75 mhz ? 3 db large signal bandwidth v o ut , dm = 2 v p -p , g = 1 25 mhz v out, dm = 2 v p - p, g = 2 22 mhz v out, dm = 2 v p - p, g = 5 19 mhz bandwidth for 0.1 db flatness v o ut , dm = 2 v p -p , g = 1 and g = 2 14.5 mhz slew rate v o ut , dm = 2 v s tep 95 v/s settling time to 0.1% v o ut , dm = 2 v s tep 34 ns overdrive recovery time g = 2, v in, dm = 6 v p -p, triangle wave 86 ns noise/harmonic performance hd2/hd3 v out, dm = 2 v p - p, f c = 1 0 khz ? 125 /?1 18 dbc v out, dm = 2 v p - p, f c = 50 khz ? 123/?126 dbc v out, dm = 2 v p - p, f c = 50 khz, g = 2 ?1 24/?1 17 dbc v o ut , dm = 2 v p - p, f c = 1 mhz ? 102/ ? 96 db c v out, dm = 2 v p - p, f c = 1 mhz , g = 2 ?1 00 /C 92 dbc imd 3 v o ut , dm = 2 v p - p, f 1 = 1.9 mhz , f 2 = 2.1 m hz ? 99 dbc input voltage noise f = 100 k hz 3.9 nv/hz input current noise f = 100 k hz 0.81 pa/hz crosstalk v o ut , dm = 2 v p - p, f c = 1 mhz ? 110 db input characteristics input offset voltage v ip = v in = v ocm = 0 v ? 0.35 0.06 + 0.35 mv input offset voltage drift t min to t max 1 . 2 v/ c input bias current ? 1. 6 ?1.1 a input bias current drift t min to t max ? 4.5 na/ c input offset current ? 500 50 +5 00 na input common - mode voltage range ?v s ? 0.2 to +v s ? 1.2 v input resistance differential 33 k ? common m ode 50 m? input capacitance 1 pf common - mode rejection ratio ( cmrr ) v os, dm /v in, cm , ?v in, cm = 1 v dc 86 119 db open - loop gain 91 99 db output characteristics output voltage swing each single - ended output ?v s + 0.1 to +v s ? 0.1 ?v s + 0. 07 to +v s ? 0. 07 v linear output current f = 1 mhz, r l, dm = 22 ?, sfdr = ? 60 dbc 4 6 ma p eak output balance error f = 1 mhz, v out, cm /v out, dm ? 65 ? 60 db
ada4940-1/ada4940-2 data sheet rev. b | page 4 of 32 v ocm to v out, cm performance table 4. parameter test conditions/comments min typ max unit v ocm dynamic performance ? 3 db small signal bandwidth v out, cm = 0.1 v p -p 36 mhz ? 3 db large signal bandwidth v out, cm = 1 v p -p 29 mhz slew rate v out, cm = 1 v p -p 52 v/s input voltage noise f = 100 khz 83 nv/hz gain v out, cm /v ocm , v ocm = 1 v 0.99 1 1.01 v/v v ocm characteristics input common - mode voltage range ?v s + 0.8 to +v s ? 0.7 v input resistance 250 k? offset voltage v os, cm = v out, cm ? v ocm ; v ip = v in = v ocm = 0 v ?6 1 +6 mv input offset voltage drift t min to t max 20 v/c input bias current ?7 +4 +7 a cmrr v os, dm /v o cm , v ocm = 1 v 86 100 db general performance table 5. parameter test conditions/c omments min typ max unit power supply operating range lfcsp 3 7 v soic 3 6 v quiescent current per amplifier enabled 1.05 1.25 1.3 8 ma quiescent current drift t min to t max 4.25 a/c disabled 13.5 28.5 a +psrr v os , dm /v s , v s = 1 v p -p 80 90 db ? psrr v os , dm /v s , v s = 1 v p -p 80 96 db disable ( disable p in ) disable input voltage disabled ( ?v s + 1) v enabled ( ?v s + 1.8) v turn - off time 10 s turn - on time 0.6 s disable pin bias current per amplifier enabled disable = +2.5 v 2 5 a disabled disable = ?2.5 v ? 10 ?5 a operating temperature range ? 40 +125 c
data sheet ada4940-1/ada4940-2 re v. b | page 5 of 32 v s = 3 v v ocm = mid supply , r f = r g = 1 k?, r l, dm = 1 k?, t a = 25c, lfcs p package, unless otherwise noted. t min to t max = ?40c to +1 2 5c. ( see figure 61 for the definition of terms .) +d in or C d in to v out, dm performance table 6 . paramete r test conditions/comments min typ max unit dynamic performance ? 3 db small signal bandwidth v out, dm = 0.1 v p -p 240 mhz v out, dm = 0.1 v p -p , g = 2 20 0 mhz v out, dm = 0.1 v p - p , g = 5 70 mhz ? 3 db large signal bandwidth v out, dm = 2 v p -p 24 mhz v out, dm = 2 v p -p , g = 2 20 mhz v out, dm = 2 v p -p , g = 5 17 mhz bandwidth for 0.1 db flatness v out, dm = 0.1 v p -p 14 mhz slew rate v out, dm = 2 v step 90 v/s settling time to 0.1% v out, dm = 2 v step 37 ns overdrive recove ry time g = 2, v in, dm = 3.6 v p -p, triangle wave 85 ns noise/harmonic performance hd2/hd3 v out, dm = 2 v p - p, f c = 50 khz (hd2/hd3) ? 115/?121 dbc v out, dm = 2 v p - p, f c = 1 mhz (hd2/hd3) ? 104/?96 dbc imd3 v out, dm = 2 v p - p, f 1 = 1.9 mhz, f 2 = 2.1 mhz ? 98 dbc input voltage noise f = 100 khz 3.9 nv/hz input current noise f = 100 khz 0.84 pa/hz crosstalk v out, dm = 2 v p - p, f c = 1 mhz ? 110 db input characteristics input offset voltage v ip = v in = v ocm = 1.5 v ? 0.4 0.06 +0.4 mv input offset voltage drift t min to t max 1.2 v/c input bias current ? 1.6 ? 1.1 a input bias current drift t min to t max ? 4.5 na/ c input offset current ?5 00 50 +5 00 na input common - mode voltage range ?v s ? 0.2 to +v s ? 1.2 v input resistance differential 33 k? common mode 50 m? input capacitance 1 pf common - mode rejection ratio (cmrr) v os, dm /v in, cm , ?v in, cm = 0.25 v dc 86 114 db open - loop gain 91 99 db output characteristics output voltage swing each single - ended output ?v s + 0.08 to +v s ? 0.08 ?v s + 0.04 to +v s ? 0.04 v linear output current f = 1 mhz, r l, dm = 26 ?, sfdr = ? 60 dbc 38 ma peak output balance error f = 1 mhz, v out, cm /v out, dm ? 65 ? 60 db
ada4940-1/ada4940-2 data sheet rev. b | page 6 of 32 v ocm to v out, cm performance table 7. parameter test conditions/comments min typ max unit v ocm dynamic performance ? 3 db small signal bandwidth v out, cm = 0 .1 v p -p 36 mhz ? 3 db large signal bandwidth v out, cm = 1 v p -p 26 mhz slew rate v out, cm = 1 v p -p 48 v/s input voltage noise f = 100 khz 92 nv/hz gain v out, cm /v ocm , v ocm = 0.25 v 0.99 1 1.01 v/v v ocm characteristics input common - mode voltage range ?v s + 0.8 to +v s ? 0.7 v input resistance 250 k? offset voltage v os, cm = v out, cm ? v ocm ; v ip = v in = v ocm = 1.5 v ?7 1 +7 mv input offset voltage drift t min to t max 20 v/c input bias current ?5 +1 +5 a cmrr v os,dm / v ocm , v ocm = 0.25 v 80 100 db general performance table 8. parameter test conditions/comments min typ max unit power supply operating range lfcsp 3 7 v soic 3 6 v quiescent current per amplifier enabled 1 1.18 1.33 ma t min to t max 4.25 a/c disabled 7 22 a +psrr v os, dm /v s , v s = 0.25 v p -p 80 90 db ? psrr v os, dm /v s , v s = 0.25 v p -p 80 96 db disable ( disable pin ) disable input voltage disabled ( ?v s + 1) v enabled (?v s + 1.8) v turn - off time 16 s turn - on time 0.6 s disable pin bias current per amplifier enabled disable = +3 v 0.3 1 a disabled disable = 0 v ?6 ?3 a operating temperature range ? 40 +125 c
data sheet ada4940-1/ada4940-2 re v. b | page 7 of 32 absolute maximum rat ings table 9 . parameter rating supply voltage 8 v v ocm v s differential input voltage 1.2 v operating temperature range ? 40 c to + 12 5c storage temperature range ? 65c to +150c lead temperature (soldering , 10 sec) 300c junction temperature 150c esd field induced charge d device model (ficdm) 1250 v human body model (hbm) 2000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for exten ded periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, ja is specified for the device soldered o n a circuit board in still air. table 10. package type ja unit 8- lea d soic (single)/4 - layer board 158 c/w 16- lead lfcsp (single) /4 - layer board 91.3 c/w 24- lead lfcsp (dual)/4 - layer board 65.1 c/w maximum power dissip ation the maximum safe power dissipation in the ada49 40 -1 / ada4940 -2 packages is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. eve n temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ada4940 -1 / ada4940 -2 . exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation a nd the power dissipated in the package due to the load drive for all outputs. the quiescent power dissipation is the voltage between the supply pins ( v s ) times the quiescent current (i s ). the load current consists of the differential and common - mode curre nts flowing to the load, as well as currents flowing through the external feedback networks and internal common - mode feedback loop. the internal resistor tap used in the common - mode feedback loop places a negligible differential load on the output. rms vol tages and currents should be considered when dealing with ac signals. airflow reduces ja . in addition, more metal directly in contact with the package leads from metal traces , through holes, ground, and power planes reduces the ja . figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for th e 8 - lead soic ( ja = 158c/w, single) the 16- lead lfcsp ( ja = 91.3 c/w , s in gle) and 24- lead lfcsp ( ja = 65.1 c / w, dual) packages on a jed ec standard 4 - layer board. ja values are approximations. 3.5 0 ?40 ?20 0 20 40 60 120 10080 maximum power dissipation (w) ambient temperature (c) 08452-004 0.5 1.0 1.5 2.0 2.5 3.0 ada4940-2 (lfcsp) ada4940-1 (lfcsp) ada4940-1 (soic) figure 3 . maximum safe power dissipation vs. ambient temperature esd caution
ada4940-1/ada4940-2 data sheet rev. b | page 8 of 32 pin configurations and function descript ions 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 disable 10 +out 9 v ocm 5 +v s 6 +v s 7 +v s 8 +v s 15 ?v s 16 ?v s 14 ?v s 13 ?v s ada4940-1 08452-101 notes 1. connect the exposed pad to ?v s or ground. figure 4 . ada4940 - 1 pin configuration (16 - lead lfcsp) 08452-003 ?in 1 v ocm 2 +v s 3 +out 4 +in 8 disable 7 ?v s 6 ?out 5 ada4940-1 figure 5. ada4940 -1 pin configuration ( soic) table 11 . ada4 940 - 1 pin function descriptions ( 16 - lead lfcsp) pin no. mnemonic description 1 ? fb negative ou tput for feedback component connection . 2 +in positive input summing node . 3 ? in negative input summing node . 4 +fb positive output for feedback component connection . 5 to 8 +v s positive supply voltage . 9 v ocm output common - mode voltage . 10 +out pos itive output for load connection . 11 ? out negative output for load connection . 12 d is able d isable pin . 13 to 16 ?v s negative supply voltage . exposed paddle (epad) connect the exposed pad to ?v s or ground . table 12 . ada4940 - 1 pin function descriptions ( 8- lead s oic) pin no. mnemonic description 1 ? in negative input summing node. 2 v ocm output common - mode voltage. 3 +v s positive supply voltage. 4 +out positive output for load connection. 5 ? out negative o utput for load connection. 6 ?v s negative supply voltage. 7 disable disable pin. 8 +in positive input summing node.
data sheet ada4940-1/ada4940-2 re v. b | page 9 of 32 ada4940-2 1 ?in1 2+ fb 1 3 +v s1 4 +v s1 5? fb2 6 +in2 15 ?v s2 16 ?v s2 17 v ocm1 18 +out1 14 disable2 13 ?out2 7 ?in2 8 +fb2 9 +v s2 11v ocm2 12 +out2 10 +v s2 21 ?v s1 22 ?v s1 23 ? fb1 24 +in1 20 disable1 19 ?out1 08452-102 notes 1. connect the exposed pad to ?v s or ground. figure 6 . ada4940 - 2 pin configuration (24 - lead lfcsp) table 13 . ada4940 - 2 pin function descriptions ( 24 - lead lfcs p) pin no. mnemonic description 1 ? in1 negative input summing node 1. 2 +fb1 positive output feedback pin 1. 3, 4 +v s1 positive supply voltage 1. 5 ? fb2 negative output feedback pin 2. 6 +in2 posit ive input summing node 2. 7 ? in2 negative input summing node 2. 8 +fb2 positive output feedback pin 2. 9, 10 +v s2 positive supply voltage 2. 11 v ocm2 output common - mode voltage 2. 12 +out2 positive output 2. 13 ? out2 negative output 2. 14 disable2 disable pin 2. 15, 16 ?v s2 negative supply voltage 2. 17 v ocm1 output common - mode voltage 1. 18 +out1 positive output 1. 19 ? out1 negative output 1. 20 disable1 disable pin 1. 21, 22 ?v s1 negative supply voltage 1. 23 ? fb1 negative output feedback pin 1. 24 +in1 positive input summing node 1. exposed paddle (epad) connect the exposed pad to ?v s or ground.
ada4940-1/ada4940-2 data sheet rev. b | page 10 of 32 typical performance characteristics t a = 25 c, v s = 2.5 v, g = 1, r f = r g = 1 k?, r t = 52.3 ? ( w hen us ed), r l = 1 k?, unless otherwise noted . see figure 59 and figure 60 for the test circuits. 3 ?9 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) 08452-006 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out, dm = 0.1v p-p g = 2, r l = 1k g = 2, r l = 200 g = 1, r l = 200 g = 1, r l = 1k figure 7 . small signal frequency response for vario us gains and loads (lfcsp) 08452-007 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 0.1 1 10 100 1000 gain (db) frequenc y (mhz) v out, dm = 0.1v p-p v s = 3.5v v s = 2.5v v s = 1.5v figure 8 . small signal frequency response for various supplies (lfcsp) figure 9 . small signal frequency response for various temperatures (lfcs p) 3 ?9 0.1 1 10 100 1000 normalized gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out = 2v p-p g = 2, r l = 1k g = 1, r l = 1k 08452-009 g = 1, r l = 200 g = 2, r l = 200 figure 10 . large signal frequency response for various gains and loads 08452-010 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 0.1 1 10 100 1000 gain (db) frequenc y (mh z) v out = 2v p-p v s = 3.5v v s = 2.5v v s = 1.5v figure 11 . large signal frequency response for various supplies 3 ?9 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out, dm = 2v p-p 08452-0 11 ?40c +25c +125c figure 12 . large signal frequency response for various temperatures 3 ?9 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out, dm = 0.1v p-p 08452-008 ?40c +25c +125c
data sheet ada4940-1/ada4940-2 re v. b | page 11 of 32 08452-012 4 3 ?9 0.1 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out, dm = 0.1v p-p lfcsp-1 lfcsp-2:ch1 lfcsp-2: ch2 soic-1 figure 13 . small signal frequency response for various packages 3 ?9 0.1 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out, dm = 0.1v p-p v ocm = 0v v ocm = +1v v ocm = ?1v 08452-013 figure 14 . small signal frequency response at various v ocm levels (lfcsp) 4 3 ?9 0.1 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out, dm = 0.1v p-p 08452-205 v ocm = ?1v v ocm = 0v v ocm = +1v figure 15 . s mall signal frequency response for various v ocm (soic) 3 ?9 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out = 2v p-p 08452-015 lfcsp-1 lfcsp-2: ch1 lfcsp-2: ch2 soic-1 figure 16 . large signal frequency response for various packages 3 ?9 0.1 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v ocm = ?1v v ocm = 0v v ocm = +1v 08452-016 v out, dm = 2v p-p figure 17 . large signal frequency response at variou s v ocm levels 4 3 ?9 0.1 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v out, dm = 0.1v p-p 08452-203 lfcsp: r l = 1k lfcsp: r l = 200 soic: r l = 1k soic: r l = 200 figure 18 . s mall signal frequency response for various packages and loads
ada4940-1/ada4940-2 data sheet rev. b | page 12 of 32 4 ?9 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 c diff = 0pf v out = 0.1v p-p c com1 = c com2 = 2pf c com1 = c com2 = 0.5pf c com1 = c com2 = 1pf c com1 = c com2 = 0pf 08452-014 figure 19 . small signal frequency response for various capacitive loads (lfcsp) 0.25 ?0.25 0.1 1000 1 10 100 normalized gain (db) frequency (mhz) ? 0.20 ? 0.15 ? 0.10 ? 0.05 0 0.05 0.10 0.15 0.20 v out, dm = 0.1v p-p g = 2, r l = 200 g = 2, r l = 1k g = 1, r l = 200 g = 1, r l = 1k 08452-018 figure 20 . 0.1 db flatness small signal frequency response for various gains and loads (lfcsp) 3 ?9 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v s = 1.5v v s = 2.5v 08452-019 v out, dm = 0.1v p-p figure 21 . v ocm small signal frequency response for various supplies 4 ?9 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 c com1 = c com2 = 0pf c com1 = c com2 = 0.5pf c com1 = c com2 = 1pf c com1 = c com2 = 2pf c diff = 0pf v out = 2v p-p 08452-017 figure 22 . large signal frequenc y response for various capacitive loads 0.25 ?0.25 0.1 1000 1 10 100 normalized gain (db) frequency (mhz) ? 0.20 ? 0.15 ? 0.10 ? 0.05 0 0.05 0.10 0.15 0.20 v out, dm = 2v p-p g = 1, r l = 1k g = 1, r l = 200 g = 2, r l = 1k g = 2, r l = 200 08452-021 figure 23 . 0.1 db flatness large signal frequency response for various gains and loads 3 ?9 1 10 100 1000 gain (db) frequency (mhz) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 v s = 1.5v v s = 2.5v 08452-022 v out, dm = 1v p-p figure 24 . v ocm large signal frequency response for various supplies
data sheet ada4940-1/ada4940-2 rev. b | page 13 of 32 ? 20 ?130 0. 01 0.1 11 0 harmonic distortion (dbc) frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 v out, dm = 2v p-p hd3, g = 2 hd3, g = 1 hd2, g = 1 08452-023 hd2, g = 2 figure 25. harmonic distortion vs. frequency for various gains (lfcsp) ? 20 ?130 0. 01 0.1 11 0 harmonic distortion (dbc) frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 v out, dm = 2v p-p hd3, r l = 200 ? hd3, r l = 1k ? hd2, r l = 1k ? hd2, r l = 200 ? 08452-020 figure 26. harmonic distortion vs. frequency for various loads (lfcsp) ? 20 ?130 ?12 0 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 08452-024 0.01 0.1 1 10 harmonic distortion (dbc) frequency (mhz) v out, dm = 2v p-p hd2, v s = 1.5v hd3, v s = 3.5v hd3, v s = 2.5v hd2, v s = 2.5v hd3, v s = 1.5v hd2, v s = 3.5v figure 27. harmonic distortion vs. frequency for various supplies (lfcsp) ? 20 ?130 0. 01 0.1 11 0 harmonic distortion (dbc) frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 08452-200 hd2, g = 1 hd3, g = 1 hd2, g = 2 hd3, g = 2 v out, dm = 2v p-p figure 28 . harmonic distortion vs. frequency vs. gain (soic) ? 20 ?130 0. 01 0.1 11 0 harmonic distortion (dbc) frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 08452-201 hd2, r l = 1k ? hd3, r l = 1k ? hd2, r l = 200 ? hd3, r l = 200 ? v out, dm = 2v p-p figure 29 . harmonic distortion vs. frequency for various loads (soic) ? 20 ?130 0. 01 0.1 11 0 harmonic distortion (dbc) frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 08452-202 hd2, 2.5v hd3, 2.5v hd2, 1.5v hd3, 1.5v v out, dm = 2v p-p figure 30 . harmonic distortion vs. frequency for various supplies (soic)
ada4940-1/ada4940-2 data sheet rev. b | page 14 of 32 ? 20 ?130 0.01 0.1 110 spurious-free dynamic range (dbc) frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 08452-030 v out, dm = 2v p-p lfcsp: r l = 1k ? lfcsp: r l = 200 ? soic: r l = 1k ? soic: r l = 200 ? figure 31. spurious-free dynamic range vs. frequency at r l = 200 and r l = 1k ? 20 ?150 ?2.5 2.5 harmonic distortion (dbc) v ocm (v) ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 v out, dm = 2v p-p hd2 at 1mhz hd2 at 100khz hd3 at 1mhz hd3 at 100khz 08452-025 figure 32. harmonic distortion vs. v ocm for 100 khz and 1 mhz, 2.5 v supplies (lfcsp) ? 20 ?130 0.01 0.1 1 10 harmonic distortion (dbc) frequency (mhz) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 hd3 at v out, dm = 8v p-p hd2 at v out, dm = 8v p-p hd2 at v out, dm = 4v p-p hd2 at v out, dm = 2v p-p hd3 at v out, dm = 2v p-p 08452-026 hd3 at v out, dm = 4v p-p figure 33. harmonic distortion vs. frequency for various v out, dm (lfcsp) ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 012345678910 harmonic distortion (dbc) v out, dm (v p-p) v s = 1.5v hd3 v s = +3v, 0v hd3 v s = +3v, 0v hd2 v s = 3.5v hd3 v s = 2.5v hd3 v s = 3.5v hd2 v s = 1.5v hd2 f = 1mhz 08452-027 v s = 2.5v hd2 figure 34. harmonic distortion vs. v out, dm for various supplies, f = 1 mhz (lfcsp) ? 20 ?140 03.0 2.5 harmonic distortion (dbc) v ocm (v) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 0.5 1.0 1.5 2.0 +v s = +3v, ?v s = 0v v out, dm = 2v p-p hd2 at 1mhz hd3 at 1mhz hd3 at 100khz hd2 at 100khz 08452-028 figure 35. harmonic distortion vs. v ocm for 100 khz and 1 mhz, 3 v supply (lfcsp) ? 20 ?140 0.01 0.1 1 10 harmonic distortion (dbc) frequency (mhz) ?120 ?130 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 v out, dm = 2v p-p 08452-029 hd3, r f = r g = 499 ? hd2, r f = r g = 499 ? hd3, r f = r g = 1k ? hd2, r f = r g = 1k ? figure 36. harmonic distortion vs. frequency for various r f and r g (lfcsp)
data sheet ada4940-1/ada4940-2 re v. b | page 15 of 32 10 0 ?120 ?110 1.5 2.5 normalized spectrum (dbc) frequency (mhz) 08452-033 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.42.3 v out, dm = 2v p-p (envelope) figure 37 . 2 mhz intermodulation distortion (lfcsp) 130 40 50 60 70 80 90 100 110 120 0.1 1 10 100 cmrr (db) frequency (mhz) 08452-100 soic lfcsp figure 38 . cmrr vs. frequency ?10 ?80 0.1 1 10 100 output balance (db) frequency (mhz) ?70 ?60 ?50 ?20 ?30 ?40 08452-032 v out, dm = 2v p-p figure 39 . output balance vs. f requency ?60 ?130 0.1 1 10 100 crosstalk (db) frequency (mhz) ?120 ?110 ?100 ?70 ?80 ?90 08452-039 channel 1 to channel 2 channel 2 to channel 1 v out, dm = 2v p-p figure 40 . crosstalk vs. frequency, ada4940 -2 120 20 0.1 1 10 100 psrr (db) frequency (mhz) 30 40 50 60 70 80 110 90 100 08452-034 +psrr ?psrr figure 41 . psrr vs. frequency 100 ?40 0 ?210 10k 100k 1m 10m 100m 1g gain (db) phase (degrees) frequency (hz) 08452-035 ?195 ?180 ?165 ?150 ?135 ?120 ?105 ?90 ?75 ?60 ?45 ?30 ?15 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 figure 42 . open - loop gain and phase vs. frequency
ada4940-1/ada4940-2 data sheet rev. b | page 16 of 32 8 ?8 ?6 ?4 0 2 4 6 ?2 0 1000 output voltage (v) time (ns) 08452-041 100 200 300 400 500 600 700 800 900 g = +2 v out, dm 2 v in figure 43 . output overdrive recovery, g = 2 100 10 1 10 100 1k 10k 100k 1m 10m input voltage noise (nv/hz) frequency (hz) 08452-037 figure 44 . voltage noise spectral density, referred to input 1.50 ?1.25 0 ?2.75 0 100 output voltage (v) disable pin voltage (v) time (s) 08452-038 ?2.50 ?2.25 ?2.00 ?1.75 ?1.50 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 10 20 30 40 50 60 70 80 90 ?out, v icm = 1v +out, v icm = 1v disable +in ?out +out ?f b +fb ?in v ocm 0.1f r1 r2 r2 +2.5v ?2.5v r1 v icm disable 0v ?2.5v figure 45 . disable pin turn - off time 2.0 ?2.0 0.5 ?0.5 0 80 voltage (v) error (%) time (ns) 08452-065 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 10 20 30 40 50 60 70 %error output input v out, dm = 2v p-p figure 46 . 0.1% settling time 100 10 1 0.1 0.01 0.1 1 10 100 output impedance (?) frequency (mhz) 08452-040 figure 47 . closed - loop output impedance magnitude vs. frequency, g = 1 2.50 ?0.25 ?2.75 0 2.0 output voltage (v) disable pin voltage (v) time (s) 08452-057 ?2.50 ?2.25 ?2.00 ?1.75 ?1.50 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 ?out, v icm = 1v disable +out, v icm = 1v +in ?out +out ?fb +fb ?in v ocm 0.1f r1 r2 r2 +2.5v ?2.5v r1 v icm disable 0v ?2.5v figure 48 . disable pin turn - on time
data sheet ada4940-1/ada4940-2 re v. b | page 17 of 32 100 ?100 0 150 output voltage (mv) time (ns) ?80 ?60 ?40 ?20 0 20 40 60 80 10 20 30 40 50 60 70 80 90 100 110 120 130 140 v out, dm = 0.1v p-p g = 2, r l = 1k g = 1, r l = 1k g = 1, r l = 200 g = 2, r l = 200 08452-042 figure 49 . small signal transient response for various gains and loads (lfcsp) ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100 1 10 120 130 140 150 output vo lt age (mv) time (ns) v out, dm = 0.1v v s = 1.5v v s = 3.5v v s = 2.5v 08452-043 figure 50 . small signal transient response for various supplies (lfcsp) 100 ?100 0 150 output voltage (mv) time (ns) ?80 ?60 ?40 ?20 0 20 40 60 80 10 20 30 40 50 60 70 80 90 100 110 120 130 140 c diff = 0pf v out, dm = 0.1v p-p c com1 = c com2 = 0pf c com1 = c com2 = 0.5pf c com1 = c com2 = 1pf c com1 = c com2 = 2pf 08452-044 figure 51 . small signal transient response for various capacitive loads (lfcsp) 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 output voltage (v) time (ns) v out, dm = 2v p-p g = 1, r l = 1k g = 1, r l = 200 g = 2, r l = 1k g = 2, r l = 200 08452-045 0 300 20 40 60 80 100 120 140 160 180 200 220 240 260 280 figure 52 . large signal transient response for various gains and loads ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 output vo lt age (v) time (ns) v out, dm = 2v p-p v s = 3.5v v s = 1.5v v s = 2.5v 08452-046 figure 53 . large signal transient response for various supplies 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 output voltage (v) time (ns) c diff = 0pf v out, dm = 2v p-p c com1 = c com2 = 0pf c com1 = c com2 = 0.5pf c com1 = c com2 = 1pf c com1 = c com2 = 2pf 08452-047 0 300 20 40 60 80 100 120 140 160 180 200 220 240 260 280 figure 54 . lar ge signal transient response for various capacitive loads
ada4940-1/ada4940-2 data sheet rev. b | page 18 of 32 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 output voltage (mv) time (ns) v out, dm = 0.1v p-p 08452-204 lfcsp-1 lfcsp-2: ch1 lfcsp-2: ch2 soic-1 figure 55 . s mall signal transient response for various packages, c l = 0 pf 100 ?100 0 150 output voltage (mv) time (ns) ?80 ?60 ?40 ?20 0 20 40 60 80 10 20 30 40 50 60 70 80 90 100 110 120 130 140 v out, dm = 0.1v p-p v s = 1.5v v s = 2.5v 08452-048 figure 56 . v ocm small signal transient response 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 output voltage (mv) time (ns) v out, dm = 0.1v p-p 08452-206 lfcsp-1 lfcsp-2: ch1 lfcsp-2: ch2 soic-1 figure 57 . small signal transient response for various packages, c l = 2 pf 1.00 ?1.00 0 300 output voltage (v) time (ns) ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 20 40 60 80 100 120 140 160 180 200 220 240 260 280 v out, dm = 1v p-p v s = 1.5v v s = 2.5v 08452-053 figure 58 . v ocm large signal transient response
data sheet ada4940-1/ada4940-2 re v. b | page 19 of 32 test circuits ada4940-1/ ada4940-2 54.9? 475? 475? 54.9? +2.5v ?2.5v 1k? 1k? 50? network analyzer output network analyzer input 1k? 1k? v ocm 52.3? 25.5? v in 08452-067 50? 50? figure 59 . equivalent basic test circuit ada4940-1/ ada4940-2 +2.5v ?2.5v 1k? 1k? 50? 1k? 475? 475? 1k? v ocm 52.3? 54.9? 54.9? 100? hp lp 2:1 50? ct v in low-pass filter dc-coupled generator dual filter 08452-056 25.5? figure 60 . test circuit for distortion measurements
ada4940-1/ada4940-2 data sheet rev. b | page 20 of 32 terminology definition of terms ada4840-1/ ada4940-2 r l, dm v out, dm r f r f r g r g +fb +in +out ?out ? + +d in +v ocm ?d in ?fb ?in 08452-090 figure 61 . circuit definitions differential voltage differential voltage refers to the difference between two no de voltages. for example, the differential output voltage (or equivalently, output differential mode voltage) is defined as v out, dm = ( v +out ? v ? out ) where v +out and v ? out refer to the voltages at the +out and ?out terminals with respect to a common refer ence. similarly, the differential input voltage is defined as v in, dm = ( +d in ? ( ?d in )) common - mode voltage (cmv) cmv refers to the average of two node voltages. the output common - mode voltage is defined as v out, cm = ( v +out + v ? out )/2 similarly , the inp ut common - mode voltage is define d as v in, cm = ( +d in + (?d in )) /2 common - mode offset voltage the common - mode offset voltage is defined as the difference between the voltage applied to the v ocm terminal and the common mode of the output voltage . v os, cm = v o ut, cm ? v ocm differential v os , differential cmrr , and v ocm cmrr t he differential mode and common - mode voltages each have their own error sources. the d ifferential offset (v os , dm ) is the voltage error between the +in and ?in terminals of the amplifier. di fferential cmrr reflects the change of v os , dm in re sponse to changes to the common - mode voltage at the input terminals +d in and ?d in . dmos, cmin, diff v v cmrr = v ocm cmrr reflects the change of v os , dm in response to changes to the commo n- mode voltage at the output terminals . dmos, ocm v v v cmrr ocm = balance balance is a measure of how well the differential signals are matched in amplitude ; the differential signals are exactly 180 apart in phase. by this definition, the output balance is the magnitude of the output common - mode voltage divided by the magnitude of the output differential mode voltage. dm out cm out v v error balance output , , =
data sheet ada4940-1/ada4940-2 rev. b | page 21 of 32 theory o f operation the ada4940 -1 / a da4940 -2 are high speed , low power differential amplifier s fabricated on analog devices advanced dielectrically isolated sige bipolar process. they provide two closely balanced differential outputs in response to either differential or single - ended input signals. an external feedback network that is similar to a voltage feedback operational amplifier sets the differential gain . the output common - mode voltage is independent of the input common - mode voltage and is set by an external voltage at the v ocm termi nal. the pnp input stage allows input common - mode voltages between the negative supply and 1 .2 v below the positive supply. a rail -to - rail output stage supplies a wide output voltage range. the disable pin can be used to reduce the s upply current of the amplifier to 13.5 a. figure 62 shows the ada4940 -1 / ada4940 -2 architecture. the differential fe edback loop consists of the differential trans - conductance g diff working through the g o output buffers and the r f /r g feedback networks. the common - mode feedback loop is set up with a voltage divider across the two differential outputs to create an output v oltage midpoint and a common - mode transconductance , g cm . 08452-058 g o c c c c r f r g g cm g diff g o r g v ref ?out +out r f +d in ?d in +in ?in v ocm figure 62 . ada4940 -1 / ada4940 -2 architectur al block the differential feedback loop forces the voltages at +in and ? in to equal each other. this fact sets the following relationships: f out g in r v r d ? ?= + f out g in r v r d + ?= ? subtracting the previous equations gives the relationship that shows r f and r g setting the differen tial gain . ( v +out ? v ? out ) = (+d in C (?d in ) ) g f r r the common - mode feedback loop drives the output common - mode voltage that is sampled at the midpoint of the output voltage divider to equal the voltage at v ocm . this results in the foll owing relationships : v +out = v ocm + 2 dm out, v v ? out = v ocm ? 2 dm out, v note that the differential amplifiers summing junction input voltages, +in and ? in , are set by both the output voltages and the input voltages . ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? + += ? + g f g out g f f in in rr r v rr r dv ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? + ?= + ? g f g out g f f in in rr r v rr r dv
ada4940-1/ada4940-2 data sheet rev. b | page 22 of 32 applications information analyzing an applica tion circuit the ada4940 -1 / ada4940 -2 use open - loop gain and negative fee dback to force their differential and common - mode output voltages in such a way as to minimize the differential and common - mode error voltages. the differential error voltage is defined as the voltage betw een the differential inputs labe led +in and ?in (see figure 61 ). for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common - mode voltage and the voltage applied to v ocm can also be assume d to be zero. starting from these two assumptions, any application circuit can be analyzed. setting the closed - loop gain the differential mode gain of the circuit in figure 61 can be determined by g f dm in dm out r r v v = , , this assumes that the input resistors (r g ) and feedback resistors (r f ) on each side are equal. estimating the outpu t noise voltage the differential output noise of the ada4940 -1 / ada4940 -2 can be estimated using the noise model in figure 63 . the input - referred noise voltage density, v nin , is modeled as a differential input, and the noise currents, i nin? and i nin + , appear between each input and ground. the noise currents are assum ed to be equal and produce a voltage across the parallel combina tion of the gain and feedback resistances. v ncm is the noise voltage density at the v ocm pin. each of the four resistors co ntributes (4ktr x ) 1/2 . table 14 summarizes the input noise sources, the multiplication factors, and the output - referred noise density terms. for more noise calculation information , go to the analog devices differential amplifier ca lculator ( diffampcalc ?) , click adidiffampcalculator.zip and follow the on - screen prompts. ada4940-1/ ada4940-2 + r f2 v nod v ncm v ocm v nin r f1 r g2 r g1 v nrf1 v nrf2 v nrg1 v nrg2 i nin+ i nin? 08452-050 figure 63 . ada4940 -1 / ada4940 -2 noise model as with conventional op amp, the output noise voltage densities can be estimated by multiplying the input - referred terms at +in and ?in by the appropriate output factor, where: ( ) 21 n | g + = 2 is the circuit noise gain. g1 f1 g1 1 rr r + = and g2 f2 g2 2 rr r + = are the feedback factors. when r f1 /r g1 = r f2 /r g2 , then 1 = 2 = , and the noise gai n becomes g f n r r g +== 1 1 note that the output noise from v ocm goes to zero in this case. the total differential output noise density, v nod , is the root -sum- square of the individual output noise terms. = = 8 1i 2 noi nod vv table 14 . output noise voltage density calculations input noise contribution input noise term input noise voltage density output multiplication factor output - referred noise voltage density term differential input v nin v nin g n v no1 = g n (v nin ) invert ing input i nin? i nin? (r g2 ||r f2 ) g n v no2 = g n [i nin? (r g2 ||r f2 )] noninverting input i nin+ i nin+ (r g1 ||r f1 ) g n v no3 = g n [i nin+ (r g1 ||r f1 )] v ocm input v ncm v ncm g n ( 1 ? 2 ) v no4 = g n ( 1 ? 2 )(v ncm ) gain resistor r g1 v nrg1 (4ktr g1 ) 1/2 g n (1 ? 2 ) v no5 = g n (1 ? 2 )(4ktr g1 ) 1/2 gain resistor r g2 v nrg2 (4ktr g2 ) 1/2 g n (1 ? 1 ) v no6 = g n (1 ? 1 )(4ktr g2 ) 1/2 feedback resistor r f1 v nrf1 (4ktr f1 ) 1/2 1 v no7 = (4ktr f1 ) 1/2 feedback resistor r f2 v nrf2 (4ktr f2 ) 1/2 1 v no8 = (4ktr f2 ) 1/2
data sheet ada4940-1/ada4940-2 rev. b | page 23 of 32 table 15 an d table 16 list several common gain setting s, recommended r esistor values, input impedance s , and output noise density for both balanced and unbalanced input configurations. ta ble 15 . differential ground - referenced input, dc - coupled, r l = 1 k? ( see figure 64 ) nominal gain (db) r f (?) r g (?) r in, dm (?) differential output noise density (nv/hz) rti (nv/hz) 0 1000 1000 2000 11.3 11.3 6 1000 500 1000 15.4 7.7 10 1000 318 636 20.0 6.8 14 1000 19 6 392 27.7 5.5 table 16 . single - ended ground- referenced input, dc - coupled, r s = 50 ?, r l = 1 k? ( see figure 65 ) nominal gain (db) r f (?) r g (?) r t (?) r in, se (?) r g1 (?) 1 differential outp ut noise density (nv/hz) rti (nv/hz) 0 1000 1000 52.3 1333 1025 11.2 11.2 6 1000 500 53.6 750 526 15.0 7.5 10 1000 318 54.9 512 344 19.0 6.3 14 1000 196 59.0 337 223 25.3 5 1 r g1 = r g + (r s ||r t ) impact of mismatches in the feedback networks e ven if the external feedb ack networks (r f /r g ) are mismatched, the internal common - mode feedback loop still forces the outputs to remain balanced. the amplitudes of the signals at each output remain equal and 180 out of phase. the input - to - output, differential mode gain varies pro portionately to the feedback mismatch, but the output balance is unaffected. as well as causing a noise contribution from v ocm , ratio - matching errors in the external resistors result in a degradation of the ability of the circuit to reject input common - mo de signals, much the same as for a four resistors difference amplifier made from a conventional op amp. in addition, if the dc levels of the input and output common - mode voltages are different, matching errors result in a small differential mode , output o ffset voltage. when g = 1, with a gr ound - referenced input signal and the output common - mode level set to 2.5 v, an output offset of as much as 25 mv (1% of the difference in common - mode levels) can result if 1% tolerance resistors are used. resistors of 1% tolerance result in a worst - case input cmrr of about 40 db, a worst - case differential mode output offset of 25 mv due to the 2.5 v level - shift, and no significant degradation in output balance error. calculating the inpu t impedance of an application circ uit the effective input impedance of a circuit depends on whether the amplifier is being driven by a single - ended or differential signal source. for balanced differential input signals, as shown in figure 64 , the i nput impedance (r in, dm ) between the inputs (+d in and ?d in ) is simply r in, dm = 2 r g . for an unbalanced, single - ended input signal (see figure 65 ), the input impedance is ( ) ? ? ? ? ? ? ? ? ? ? ? ? + ? = fg f g se in rr r r r 2 1 , +v s ada4940-1/ ada4940-2 +in ?in r f r f +d in ?d in v ocm r g r g v out, dm 08452-051 figure 64 . ada4940 -1 / ada4940 -2 configured for balanced (differential) inputs r t r s ada4940-1/ ada4940-2 +v s r f r g r s r g r f v ocm r t v out, dm 08452-052 +in ?in figure 65. ada4940 -1 / ada4940 -2 configured for unbalanced (single - ended) input the input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common - mode signal, partially bootstrapping the voltage across the input resistor r g1 .
ada4940-1/ada4940-2 data sheet rev. b | page 24 of 32 terminating a single - ended input this se c tion describes how to properly terminate a s ingle - ended input to the ada4940 -1 / ada4940 -2 with a gain of 1, r f = 1 k? and r g = 1 k?. an example using an input source with a terminated output voltage of 1 v p - p and source resistance of 50 ? illustrates the three steps that must be followed. b ecause the terminated output voltage of the source is 1 v p - p, the open - circuit output voltage of the source is 2 v p - p. the source shown in figure 66 indicates this open - circuit voltage. r s 50? v s 2v p-p r in, se 1.33k? ada4940-1 ada4940-2 r l v out, dm +v s ?v s r g 1k? r g 1k? r f 1k? r f 1k? v ocm 08452-059 figure 66 . calculating single - ended input impedance, r in 1. the input impedance is calculated by k .33 1 )1000 1000(2 1000 1 1000 )(2 1 , = ? ? ? ? ? ? ? ? ? ? ? ? + ? = ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g se in rr r r r 2. to match the 50 ? source resistance, calculate the termin a tion resistor, r t , using r t ||1.33 k? = 50 ?. the closest standard 1% value for r t is 52.3 ?. ada4940-1 ada4940-2 r l v out, dm +v s ?v s r s 50? r g 1k? r g 1k? r f 1k? r f 1k? v ocm v s 2v p-p r in, se 50? r t 52.3 ? 08452-060 figure 67 . adding termination resistor r t 3. figure 67 shows that the effective r g in the upper feedback loop is now greater than the r g in the lower loop due to the addition of the termination resistors. to compensate for the imbalance of the gain resistors, add a correction resistor (r ts ) in series with r g in the lower loop. r ts is the thevenin equivalent of the source resi s tance, r s , and the termination resistance, r t , and is equal to r s ||r t . r s 50? v s 2v p-p r t 52.3 ? r th 25.5? v th 1.02v p-p 08452-061 figure 68 . calculating the thevenin equivalent r ts = r th = r s ||r t = 25. 5 ?. note that v th is greater than 1 v p - p, which was obtained with r t = 50 ?. the modified circuit with the thevenin equivalent (closest 1% value used for r th ) of the terminated source and r ts in the lower feedback loop is shown in figure 69 . ada4940-1 ada4940-2 r l v out, dm +v s ?v s r th 25.5? r g 1k? r g 1k? r f 1k? r f 1k? v ocm v th 1.02v p-p r ts 25.5 ? 08452-062 figure 69 . thevenin equivalent and matched gain resistors figure 69 presents a tractable circuit with matched feedback loops that can be easily evaluated. it is useful to point out two effects that occur with a terminated input. the first is that the value of r g is increased in both loops, lowering the overall closed - loop gain. the second is that v th is a little larger than 1 v p - p, as it would be if r t = 50 ? . these two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 k?), the effects essentially cancel each other out. for small r f and r g , or high gains, however, the diminished closed - loop gain is not cance l led completely by the inc reased v th . this can be seen by evaluating figure 69 . the desired differential output in this example is 1 v p - p because the terminated input signal was 1 v p - p and the closed - loop g ain = 1. the actual differential output voltage, however, is equal to (1.0 2 v p - p)( 1000 / 10 25 .5) = 0.9 96 v p - p. this is within the tolerance of the resistors , so no change to the feedback resistor , r f , is required. input common - mode voltage range the ada4940 -1 / ada4940 -2 input common - mode range is shifted down by approximately 1 v be , in contrast to other adc drivers with centered input ranges , such as the ada4939 -x . the downward - shifted input common - mode range is especially suited to dc - coupled, single - ended - to - differential, and single - supply applications. for 2. 5 v or +5 v supply operation, the input common - mode rang e at the summing nodes of the amplifier is specified as ? 2. 7 v to + 1.3 v or ? 0.2 v to 3.8 v , and is specified as ? 0.2 v to + 1.8 v with a + 3 v supply.
data sheet ada4940-1/ada4940-2 rev. b | page 25 of 32 input and output capacitive ac coupling although the ada 4940 -1 / ada4940 -2 is best suited to dc - coupled applications, it is nonetheless possible to use it in ac - coupled circuits. input ac coupling capacitors can be inserted between the source and r g . this ac coupl ing blocks the flow of the dc common - mode feedback current and causes the ada4940 -1 / ada4940 -2 dc input common - mode voltage to equal the dc output common - mode voltage. these ac coupling capacitors must be placed in both loops to keep the feedback factors matched. output ac coupling capacitors can be placed in series between each output and its respective load. setting the output c ommon- mode voltage the v ocm pi n of the ada4940 -1 / ada4940 -2 is internally biased at a voltage approximately equal to the midsupply point, [(+v s ) + (?v s )]/2. relying on this internal bias re sults in an output common - mode voltage that is within approximately 100 mv of the expected value. in cases where more accurate control of the output common - mode level is required, it is recommended that an external source, or resistor divider (10 k? or gre ater resistors), be used. the output common - mode offset listed in the specifications section assumes that the v ocm input is driven by a low impedance voltage source. it is also possible to connect the v ocm input to a common - mode level (cml) output of an adc. however, care must be taken to ens ure that the output has sufficient drive capability. the input impedance of the v ocm pin is approximately 250 k?. disable pin the ada4940 -1 / ada4940 -2 feature a disable pin that can be used to minimize the quiescent current consumed when the device is not being used. disable is ass erted by applying a low logic level to the disable pin . the thres h old between high and low logic levels is nominally 1.4 v above the negative supply rail. see table 5 and table 8 for the threshold limits. the disable pin features an internal pull - up network that enables the amplifier for normal operation. the ada4940 -1 / ada4940 -2 disable pin can be left floating (that is, no external connection is required) and does not require an external pull - up resistor to ensure normal on operation (see figure 70 ). when the ada4940 -1 / ada4940 -2 is disabled, the output is high impedance. note that the outputs are tied to the inputs through the feedback resistors and to the source using the gain resistors. in addition, there are back - to - back diodes on the input pins that limit the differential voltage to 1.2 v. 08452-063 disable amplifier bias current ?v s +v s figure 70 . disable pin circuit driving a capacitive load a purely capacitive load reacts with the bond wire and pin inductance of the ada4940 -1 / ada4940 -2 , resulting in high frequency ringin g in the transient response and loss of phase margin. one way to minimize this effect is to place a resistor in series with each output to buffer the load capacitance. the resistor and load capacitance form a first - order, low - pass filter; therefore, the re sistor value should be as small as possible. in some cases, the adcs require small series resistors to be added on their inputs. figure 71 illustrates the c a pacitive load vs. the series resist ance required to maint ain a minimum 45 of phase margin. 120 0 5 100 10 1000 08452-064 20 40 60 80 100 series resistance (?) load capacitance (pf) +in ?out +out ?fb +fb ?in v ocm 0.1f r s r s r1 c l c l r2 r4 +2.5v ?2.5v r3 v in figure 71 . capacitive load vs. series resistance (lfscp)
ada4940-1/ada4940-2 data sheet rev. b | page 26 of 32 driving a high precision adc the ada4940 -1 / ada4940 -2 are ideally suited for broadband dc - coupled applications. the circuit in figure 73 shows a front - end connection for an ada4940 -1 driving an ad7982 , which is an 18 - bit, 1 msps succ essive approximation, analog - to - digital converter (adc) that operates from a single power supply, 3 v to 5 v. it contains a low power, high speed, 18 - bit sampling adc and a versatile serial interface port. the reference voltage, ref, is applied externally and can be set independent of the supply voltage. as shown in figure 73 , the ada4940 -1 is dc - coupled on the input and th e output, which eliminates the need for a transformer to drive the adc. the amplifier performs a single- ended - to - differential conversion if needed and level shifts the input signal to match the input common mode of the adc. the ada4940 -1 is configured with a dual 7 v supply (+6 v and ?1 v) and a gai n that is set by the ratio of the feedback resistor to the gain resistor. in addition, the circuit can be used in a single - ended - input - to - differential output or di fferential - input - to - differential outpu t configuration. if needed, a termination resistor in parallel with the source i nput can be used. whether the input is a single - ended input or differential, the input impedance of the amplifier can be calculated as sho wn in the terminating a single - ended input section. if r1 = r2 = r3 = r4 = 1 k?, the single - ended input impedance is approximately 1.33 k, which, in parallel with a 52.3 termination resistor , provides a 50 termination for the source. an additional 25.5 (1025.5 total) at the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. however, if a differential source input is used, the differential input im pedance is 2 k. in this case, two 52.3 termination resistors are used to terminate the inputs. in this example, the signal generator has a 10 v p - p symmetric, ground - referenced bipolar output. the v ocm input is bypassed for noise reduction and set exter nally with 1% resist ors to 2.5 v to maximize the output dynamic range . with an output common - mode voltage of 2.5 v, each ada4940 -1 output swings between 0 v and 5 v, opposite in phase, providing a gain of 1 and a 10 v p - p differential signal to the adc input. the differential rc section between the ada4940 -1 output and the adc provides single - pole, low - pass filtering with a corner frequency of 1.79 mhz and extr a buffering for the current spikes that are output from the adc input when its sample - and - hold (sha) capacitors are discharged. the total system power in figure 73 is under 35 mw . a large portion of that power is the current coming from supplies to the output, which is set at 2.5 v, going back to the input through the feedback and gain resistors. to reduce that power to 25 mw , increase the value of the feedback and gain resistor from 1 k to 2 k and set the value of the resistors r5 and r6 to 3 k? . the adr435 i s used to regulate the +6 v supply to +5 v , which ends up powering the adc and setting the reference voltage for the v ocm pin. figure 72 shows the fft of a 20 k hz differential input tone sampled at 1 msps. the second and third harmonics are down at ?118 dbc and ?122 dbc. 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20k 40k 60k 80k 100k amplitude (db) frequency (hz) 08452-069 figure 72 . distortion measurement of a 20 khz input tone ( cn- 0237 ) 08452-066 33? 33? 10f r1 ?d in +2.5v +5v +6v ?1v r2 r4 +6v ref vdd gnd in+ in? ad7982 2.7nf 2.7nf ?in +out ?out +in r3 +d in adr435 0.1f r6 r5 serial interface ?fb +fb ada4940-1 v ocm figure 73 . ada4940 -1 (lfcsp) driving the ad7982 adc
data sheet ada4940-1/ada4940-2 rev. b | page 27 of 32 layout, grounding, and bypassing as a high speed device, the ada4940 -1 / ada4940 -2 are sensitive to the pcb environment in which they operate. realizing their superior performance requires attention to the details of high speed pcb design. ada4940 - 1 lfcsp example t he first requirement is a solid ground plane that covers as much of the board area around the ada4940 -1 as possible. however, clear the area near the feedback resi stors (r f ), gain resistors (r g ), and the input summing nodes (pin 2 and pin 3) of all ground and power planes (see figure 74 ). clearing the ground and power planes minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. the thermal resistance, ja , is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4 - layer circuit board, as described in eia/jesd 51- 7. 08452-086 fi gure 74 . ground and power plane voiding in vicinity of r f and r g bypass t he power supply pins as close to the device as possible and directly to a nearby ground plane. use h igh frequency ceramic chip capacitors . use two parallel b ypass capacitors (1000 pf and 0.1 f) for each supply. place t he 1000 pf capacitor closer to the device. further away, provide low frequency bypassing using 10 f tantalum capacitors from each supply to ground. ensure that s ignal routing is short and dire ct to avoid parasitic effects. wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. when routing differential signals over a long distance, ensure that pcb traces are close together, and twist any differentia l wiring such that loop area is minimized. doing this reduces radiated energy and makes the circuit less susceptible to interference. 1.30 0.80 0.80 1.30 08452-087 figure 75 . recommended pcb thermal attach pad dimensions ( mm ) 0.30 plated via hole 1.30 ground plane power plane bottom metal top metal 08452-088 figure 76 . cross - section of 4 - layer pcb showing thermal via connection to buried ground plane (dimensions in mm )
ada4940-1/ada4940-2 data sheet rev. b | page 28 of 32 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. 072208-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 77 . 16 - lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp - 16 -2) dimensions shown in millimeters control ling d imensions are in millimeters; inch dimensi ons (in parentheses) are rounded-off millimeter e quiva lents for reference only and are not appropri at e for use in design. compliant to jedec standards m s-012-aa 012407-a 0.25 (0.0098) 0.1 7 ( 0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1 .75 (0.0688) 1.35 (0.0532) seating p lane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4 .80 ( 0.1890) 4.00 (0.1574) 3.80 (0.1 497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2 284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0 .10 figure 78 . 8 - lead standard small outline package [soic _n ] (r- 8) dimensions shown in millimeters and (inches)
data sheet ada4940-1/ada4940-2 rev. b | page 29 of 32 compliant to jedec standards mo-220-vggd-8 1 24 6 7 13 19 18 12 2.65 2.50 sq 2.35 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min exposed pa d (bo tt om view) 082908-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 79 . 24 - lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp - 24 -3) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity branding ada4940 - 1acpz -r2 ? 40c to +1 2 5c 16- lead lfcsp_v q cp -16 -2 250 h2 9 ada4940 - 1acpz -rl ? 40c to +125c 16- lead lfcsp_v q cp -16 -2 5,000 h29 ada4940 - 1acpz -r7 ? 40c to +125c 16- lead lfcsp_v q cp -16 -2 1,500 h29 ada4940 - 1acp- ebz e valuation board ada4940 -1a rz ? 40c to +125c 8- lead s oic _n r-8 98 ada4940 -1a rz- rl ? 40c to +125c 8- lead s oic _n r-8 2,500 ada4940 -1a rz- r7 ? 40c to +125c 8- lead s oic _n r-8 1, 0 00 ada4940 -1a r- ebz evaluation board ada4940 - 2acpz -r2 ? 40c to +125c 24- lead lfcsp_vq cp -24 -3 250 ada4940 - 2acpz -rl ? 40c to +125c 24- lead lfcsp_vq cp -24 -3 5,00 0 ada4940 - 2acpz -r7 ? 40c to +125c 24- lead lfcsp_vq cp -24 -3 1,500 ada4940 - 2acp- ebz e valuation board 1 z = rohs compliant part.
ada4940-1/ada4940-2 data sheet rev. b | page 30 of 32 notes
data sheet ada4940-1/ada4940-2 rev. b | page 31 of 32 notes
ada4940-1/ada4940-2 data sheet rev. b | page 32 of 32 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08452 -0- 3/12(b)

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